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	<title><![CDATA[asic and fpga Resources | BNET]]></title>
	<link><![CDATA[http://resources.bnet.com/topic/asic+and+fpga.html]]></link>
	<description><![CDATA[White papers, case studies, business articles, and blog posts relating to asic and fpga]]></description>
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		<title><![CDATA[Synplicity's Synplify DSP 3.6 Software Speeds DSP Algorithm Design for ASICs and FPGAs]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2008_April_1/ai_n24965729]]></link>
		<description><![CDATA[New Architectural Optimizations and Intellectual Property Provide Significant Advantages]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Tue, 01 Apr 2008 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/dsp.html"><![CDATA[DSP]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[Aldec Releases Riviera-PRO Targeting ASIC/FPGA Verification Market]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2007_Oct_11/ai_n27405090]]></link>
		<description><![CDATA[HENDERSON, Nev. -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced today the release of Riviera-PRO 2007.10, with expanded SystemVerilog Verification construct support and improved performance of VHDL, Verilog and mixed RTL simulation. This mixed-language design simulation environment supports VHDL, Verilog,...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 11 Oct 2007 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[Synplicity's Certify Software Eases ASIC Prototyping with Support for Xilinx Virtex-5 FPGAs]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2007_Jan_29/ai_n17155846]]></link>
		<description><![CDATA[Software Extends Automation of ASIC Prototyping Flow; Enhances Quick Partitioning Technology]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 29 Jan 2007 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/software.html"><![CDATA[software]]></category>
		<category domain="http://resources.bnet.com/topic/xilinx+inc..html"><![CDATA[Xilinx Inc.]]></category>
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		<title><![CDATA[Atmel Extends Its FPGA to ASIC Conversion Service for Space Applications.]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb5570/is_200505/ai_n24144156]]></link>
		<description><![CDATA[NANTES, France, May 3 /PRNewswire/ --    NANTES, France, May 3 /PRNewswire/ --  ]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Tue, 03 May 2005 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2005_April_4/ai_n13501768]]></link>
		<description><![CDATA[SAN JOSE, Calif. -- ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-SyncR program to improve the complete design flow between Synopsys Design CompilerR FPGA DC FPGA Synthesis software, the VCSR comprehensive RTL verification solution and ProDesign CHIPitR ASIC...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 04 Apr 2005 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/prodesign.html"><![CDATA[ProDesign]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[Altera Takes Aim at ASICs (Electronic News)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb5934/is_200411/ai_n23914869]]></link>
		<description><![CDATA[Aimed at eventually replacing ASICs in high-density, high-performance applications, Altera Corp. today said it is shipping its 90nm Stratix II EP2S130 device, what it says is the world's biggest FPGA with 132,540 equivalent logic elements -- more th      Aimed at eventually replacing ASICs in high-density,...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 29 Nov 2004 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/altera+corp..html"><![CDATA[Altera Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ALTR</category>
		<category domain="tickers">ALTR</category>
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		<title><![CDATA[True Circuits Invites ASIC, FPGA & SoC Designers to the ARM Developers' Conference to Learn More About Using Hard Timing Macros in ARM Cores]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2004_Oct_15/ai_n6238894]]></link>
		<description><![CDATA[October 19, 20 and 21st at the Santa Clara Convention Center]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Fri, 15 Oct 2004 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/arm.html"><![CDATA[ARM]]></category>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[Synopsys again tries its hand at FPGA synthesis.(leading edge)(Brief Article)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200406/ai_n17459590]]></link>
		<description><![CDATA[FPGA DEVICES offer enough speed and size to be viable tools for  ASIC prototyping and, in many cases, substitute for ASIC devices for  short periods during product introduction. A1 though Synopsys is the  undisputed market leader in ASIC synthesis, it    FPGA DEVICES offer enough...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 10 Jun 2004 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[Mentor Graphics Catapult C Synthesis Proven to Create Optimized ASIC/FPGA Hardware from Untimed C++ Up to 20 Times Faster]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2004_May_31/ai_n6048636]]></link>
		<description><![CDATA[Business Editors/High-Tech Writers]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 31 May 2004 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/c.html"><![CDATA[C]]></category>
		<category domain="http://resources.bnet.com/topic/c%252b%252b.html"><![CDATA[C++]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/hardware.html"><![CDATA[hardware]]></category>
		<category domain="http://resources.bnet.com/topic/mentor+graphics+corp..html"><![CDATA[Mentor Graphics Corp.]]></category>
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		<category domain="http://rss.financialcontent.com/stocksymbol">MENT</category>
		<category domain="tickers">MENT</category>
	</item>
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		<title><![CDATA[Product lowers third-generation-device-development costs.(Analog Devices ADSP-TS101S)(Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200110/ai_n17512893]]></link>
		<description><![CDATA[USING ANALOG DEVICES' ADSP-TS101S DSP to develop  third-generation base-station systems costs significantly less than  using a DSP for symbol-rate processing or using ASICs and FPGA  implementations for chip-rate processing. The TS101S includes  instr    USING ANALOG DEVICES' ADSP-TS101S DSP to develop  third-generation base-station...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 11 Oct 2001 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/analog+devices+inc..html"><![CDATA[Analog Devices Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ADI</category>
		<category domain="tickers">ADI</category>
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		<title><![CDATA[FPGA family takes integration "serialously".(Product Information)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200010/ai_n17471284]]></link>
		<description><![CDATA[QUICKLOGIC, WITH ITS QUICKSD DEVICES, continues to lead the  programmable-logic charge into ASIC/FPGA hybrids, which the company  calls Embedded Standard Products. With as many as eight SERDES  (serializer/deserializer, along with multiplexer/demultip    QUICKLOGIC, WITH ITS QUICKSD DEVICES, continues to lead the  programmable-logic charge into...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 12 Oct 2000 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/product+information.html"><![CDATA[product information]]></category>
		<category domain="http://resources.bnet.com/topic/quicklogic+corp..html"><![CDATA[QuickLogic Corp.]]></category>
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		<category domain="http://rss.financialcontent.com/stocksymbol">QUIK</category>
		<category domain="tickers">QUIK</category>
	</item>
	<item>
		<title><![CDATA[Tool certifies synthesis.(THE CERTIFY RTL-verification tool from Synplicity)(Brief Article)(Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200008/ai_n17470776]]></link>
		<description><![CDATA[A NEW VERSION OF THE CERTIFY RTL-verification tool from Synplicity  combines partitioning with FPGA synthesis to enable ASIC designers to  prototype their designs with FPGAs. Certify enhancements include a new  user interface and automatic translation    A NEW VERSION OF THE CERTIFY RTL-verification tool from...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 03 Aug 2000 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/synthesis.html"><![CDATA[synthesis]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[Simtek Acquires ASIC House and Buys Xicor Devices.(Company Business and Marketing)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb5759/is_200006/ai_n23779049]]></link>
		<description><![CDATA[Simtek, a provider of re-programmable nonvolatile semiconductor  memories, acquired Colorado Springs-based Integrated Logic Systems, Inc.  ILSI. ILSI specializes in providing low-cost metal programmable gate  array MPGA replacements for FPGAs suppli  Simtek, a provider of re-programmable nonvolatile semiconductor  memories, acquired Colorado Springs-based Integrated Logic Systems, Inc....]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 01 Jun 2000 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/marketing.html"><![CDATA[marketing]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[Xilinx Announces Record-breaking Demonstration of Data Encryption Standard; Run-time Reconfiguration Pushes FPGA Performance Past ASICs]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2000_April_28/ai_61806976]]></link>
		<description><![CDATA[Business Editors/High-tech Writers]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Fri, 28 Apr 2000 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/des.html"><![CDATA[DES]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/xilinx+inc..html"><![CDATA[Xilinx Inc.]]></category>
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		<title><![CDATA[Xilinx and Qualis Partner to Develop Internet-enabled Design Reuse Methodology for ASIC and FPGA Designers]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2000_March_20/ai_60267375]]></link>
		<description><![CDATA[Business Editors & High-Tech Writers]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 20 Mar 2000 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/internet.html"><![CDATA[Internet]]></category>
		<category domain="http://resources.bnet.com/topic/xilinx+inc..html"><![CDATA[Xilinx Inc.]]></category>
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		<category domain="http://rss.financialcontent.com/stocksymbol">XLNX</category>
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		<title><![CDATA[Xilinx and Synopsys Enable ASIC Designers' Adoption of Xilinx FPGAs]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2000_March_3/ai_59712112]]></link>
		<description><![CDATA[Business Editors & High-Tech Writers]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Fri, 03 Mar 2000 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/xilinx+inc..html"><![CDATA[Xilinx Inc.]]></category>
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		<title><![CDATA[Xilinx and Synopsys Enable ASIC Designers Adoption of Xilinx FPGAs]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2000_March_3/ai_59712218]]></link>
		<description><![CDATA[Business Editors/High-Tech Writers]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Fri, 03 Mar 2000 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/xilinx+inc..html"><![CDATA[Xilinx Inc.]]></category>
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	<item>
		<title><![CDATA[ASICs get "embed" with FPGAs.(Brief Article)(Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199908/ai_n17459505]]></link>
		<description><![CDATA[LSI Logic is enhancing its G 12 0.18-[micro]m-drawn process  portfolio with programmable-logic-core capability in partnership with  Adaptive Silicon (www.adaptivesilicon.com). The ASIC vendor believes  that its approach is ideal for embedding because     LSI Logic is enhancing its G 12 0.18-[micro]m-drawn process  portfolio with...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 19 Aug 1999 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/lsi+logic+corp..html"><![CDATA[LSI Logic Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[Actel Implements MX Device Price Reductions of Up to 50 Percent; Lowered Prices Further Enhance FPGAs Appeal as ASIC Alternative]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_1998_Oct_5/ai_53054203]]></link>
		<description><![CDATA[SUNNYVALE, Calif.--BUSINESS WIRE--Oct. 5, 1998--Actel Corporation (Nasdaq: ACTL) announced that list prices for its MX family of field programmable gate arrays FPGAs will be reduced up to 50 percent. MX price reductions provide designers with an opportunity to quickly achieve production goals and differentiate their products from the competition with...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 05 Oct 1998 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/actel.html"><![CDATA[Actel]]></category>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
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		<category domain="http://rss.financialcontent.com/stocksymbol">ACTL</category>
		<category domain="tickers">ACTL</category>
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		<title><![CDATA[Altera FPGA to ASIC Conversion in Less Than Two Weeks]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_1998_June_29/ai_50127205]]></link>
		<description><![CDATA[SANTA CLARA, Calif.--BUSINESS WIRE--June 29, 1998--Santa Clara, Calif., startup, Clear Logic, Inc. today introduced a new member of its CL8000 family of laser-configured ASICs (LASICTMs), the 6,000 gate CL8636.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 29 Jun 1998 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/altera+corp..html"><![CDATA[Altera Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ALTR</category>
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