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- Structured ASIC Fallout: Synplicity Exits Market (Electronic News)
- Based on LSI Logic's recent decision http://www.reed-electronics.com/electronicnews/article/CA6313947 to pull its RapidChip platform ASIC product from the market, Sunnyvale, Calif.-based programmable logic design tool provider Synplicity Inc. said T Based on LSI Logic's recent decision http://www.reed-electronics.com/electronicnews/article/CA6313947 to pull its RapidChip platform ASIC product from the market,...
- Research articles 2006-04-03
- Synplicity ASIC Synthesis Product Offers Support for Leading ASIC Design Tools and IP Libraries; New Synplify ASIC Product Flow-Tested With Physical Design and Test Tools
- Business Editors/High-Tech Writers
- Research articles 2001-06-04
- Mentor Graphics Adds Distributed Processing Features to ASIC Prototyping Tool
- Business Editors & Technology Writers
- Research articles 2002-08-12
- ASIC makers step up software support; Fujitsu, Harris, Motorola introduce third-party suites. (application-specific integrated circuits) (product announcement)
- ASIC makers step up software support Three major ASIC suppliers have introduced design software suites that employ third-party and proprietary tools linked by a common user interface and operating protocol. Back-end data management differs, as ASIC makers step up...
- Research articles 1989-08-24
- Synopsys, Xilinx Target ASIC Prototypers (Electronic News)
- Synopsys Inc., which pioneered the logic synthesis tool, is lending its expertise to ASICs prototyping engineers with support for the Xilinx Virtex-4 family of FPGAs in its Design Compiler FPGA tool and ISE 6.3i place and route software. Synopsys Inc., which pioneered the logic synthesis...
- Research articles 2004-10-04
- ASIC Semiconductor Supports Mentor Graphics Design for Test Tools
- SANTA CLARA, Calif.--BUSINESS WIRE--Nov. 25, 1996--ASIC Semiconductor Inc., the first full-service ASIC vendor that will also license its libraries, is now supporting design for test DFT methodologies and tools from Mentor Graphics (Beaverton, Ore.).
- Research articles 1996-11-25
- Hier Design Adds NVIDIA to Growing Customer List; PlanAhead Used as ASIC Prototyping Tool
- Business Editors/High-Tech Writers
- Research articles 2004-04-26
- Synplicity and Lightspeed Semiconductor Ink Agreement to Develop Custom ASIC Synthesis Tools
- Business Editors/High-Tech Writers
- Research articles 2003-03-14
- Telairity Adopts Circuit Semantics' Characterization Tools to Streamline IP and ASIC Design Flow Methodology
- Business Editors/High-Tech Writers
- Research articles 2002-12-02
- IDE system seeks cut in ASIC development time - NEC Electronics and Microsystem Synthesis KO-Integrated Development Environment development tool - Company Business and Marketing
- Mountain View, Calif.--NEC Electronics and Microsystem Synthesis Inc. today will introduce a development tool that integrates user-defined logic, standard macros and microcontroller cores into a single application specific integrated circuit ASIC.
- Research articles 1996-08-12
- NEC Electronics Selects Synplicity's Verification Tool for New ASIC/SOC Design Methodology; NEC is First ASIC Vendor to Endorse RTL Prototyping
- Business Editors/High Tech Writers
- Research articles 2000-05-15
- Synplicity Enhances ASIC Prototyping and Partitioning Solution With Availability of Certify 2.1; Tool Enables Rapid Hardware Prototypes From RTL Code
- SUNNYVALE, Calif.--BUSINESS WIRE--Oct. 4, 1999--
- Research articles 1999-10-04
- Leading ASIC Companies Pledge Library Support for Cadence Envisia Ambit Synthesis Tool; Tool Chosen for Accuracy and Superior Performance
- SAN JOSE, Calif.--BUSINESS WIRE--Dec. 17, 1999--
- Research articles 1999-12-17
- IBM cuts E-beam ASIC fab in sub-micron, CMOS shift - reduction in electron-beam application specific integrated circuit production and change from bipolar to complementary metal oxide semiconductor technology - Lithography Tools
- EAST FISHKILL, N.Y.--IBM, as part of a significant reordering of its semiconductor production efforts, is sharply cutting its use of direct-write electron-beam lithography for production of low-volume application specific ICs.
- Research articles 1992-10-26
- Everything's coming up ASICs. (application-specific integrated circuits) (includes related articles on the ASIC business)
- Everything's coming up ASICs Creating successful application-specific ICs ASICs--standard cells, gate arrays, and programmable logic devices PLDs--doesn't end with technology prowess. The successful vendor will also possess a broad product Everything's coming up ASICs ...
- Research articles 1988-11-17
- Electronic Design Automation.(Technology Information)
- Verilog simulator * Stand-alone direct-compile simulator complies with IEEE-1364-95 standard * Provides HDL, state machine, and block diagram/schematic editors * Includes a project manager, automatic testbench generator, waveform v ...
- Research articles 2000-10-26
- ASIC International Uses Cadence Synthesis Tool to Compile 2.4-Million Gate Design; Ultra High Capacity of Envisia Ambit Product Enables Chip-Level Synthesis
- SAN JOSE, Calif.--BUSINESS WIRE--Sept. 7, 1999--
- Research articles 1999-09-07
- Tool certifies synthesis.(THE CERTIFY RTL-verification tool from Synplicity)(Brief Article)(Product Announcement)
- A NEW VERSION OF THE CERTIFY RTL-verification tool from Synplicity combines partitioning with FPGA synthesis to enable ASIC designers to prototype their designs with FPGAs. Certify enhancements include a new user interface and automatic translation A NEW VERSION OF THE CERTIFY RTL-verification tool from...
- Research articles 2000-08-03
- Crosspoint Solutions joins Intergraph Electronics' ASIC Partners program, supports Version 14.0 of VeriBest Design Tools
- MILPITAS, Calif.--BUSINESS WIRE--Nov. 1, 1995--Crosspoint Solutions Inc. announced that it has become an "ASIC Partner" in Intergraph Electronics' VeriBest ASIC Alliance Partner program, and as part of this alliance, supports the new Release V14.0 of Intergraph Electronics' VeriBest CAD Design Tools.
- Research articles 1995-11-01
- Mentor Graphics' SST Velocity Static Timing Tool Now Supported in Fujitsu's ASIC Design Kit
- WILSONVILLE, Ore.--BUSINESS WIRE--Dec. 16, 1998--Mentor Graphics Corporation (Nasdaq:MENT) today announced that its SST Velocitytm static timing analysis technology is now supported in Fujitsu's SystemFAME ASIC design kit.
- Research articles 1998-12-16
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