<![CDATA[asic and tool Resources | BNET]]> en-us <![CDATA[Structured ASIC Fallout: Synplicity Exits Market (Electronic News)]]> Mon, 03 Apr 2006 00:00:00 -0700 <![CDATA[Synopsys, Xilinx Target ASIC Prototypers (Electronic News)]]> Mon, 04 Oct 2004 00:00:00 -0700 XLNX XLNX <![CDATA[Hier Design Adds NVIDIA to Growing Customer List; PlanAhead Used as ASIC Prototyping Tool]]> Mon, 26 Apr 2004 00:00:00 -0700 NVDA NVDA <![CDATA[Synplicity and Lightspeed Semiconductor Ink Agreement to Develop Custom ASIC Synthesis Tools]]> Fri, 14 Mar 2003 00:00:00 -0800 <![CDATA[Telairity Adopts Circuit Semantics' Characterization Tools to Streamline IP and ASIC Design Flow Methodology]]> Mon, 02 Dec 2002 00:00:00 -0800 <![CDATA[Mentor Graphics Adds Distributed Processing Features to ASIC Prototyping Tool]]> Mon, 12 Aug 2002 00:00:00 -0700 MENT MENT <![CDATA[Synplicity ASIC Synthesis Product Offers Support for Leading ASIC Design Tools and IP Libraries; New Synplify ASIC Product Flow-Tested With Physical Design and Test Tools]]> Mon, 04 Jun 2001 00:00:00 -0700 <![CDATA[Electronic Design Automation.(Technology Information)]]> Thu, 26 Oct 2000 00:00:00 -0700 CDNS MENT CDNS,MENT <![CDATA[Tool certifies synthesis.(THE CERTIFY RTL-verification tool from Synplicity)(Brief Article)(Product Announcement)]]> Thu, 03 Aug 2000 00:00:00 -0700 <![CDATA[NEC Electronics Selects Synplicity's Verification Tool for New ASIC/SOC Design Methodology; NEC is First ASIC Vendor to Endorse RTL Prototyping]]> Mon, 15 May 2000 00:00:00 -0700 NIPNY 6723 NIPNY,6723 <![CDATA[Leading ASIC Companies Pledge Library Support for Cadence Envisia Ambit Synthesis Tool; Tool Chosen for Accuracy and Superior Performance]]> Fri, 17 Dec 1999 00:00:00 -0800 CDNS CDNS <![CDATA[Synplicity Enhances ASIC Prototyping and Partitioning Solution With Availability of Certify 2.1; Tool Enables Rapid Hardware Prototypes From RTL Code]]> Mon, 04 Oct 1999 00:00:00 -0700 <![CDATA[ASIC International Uses Cadence Synthesis Tool to Compile 2.4-Million Gate Design; Ultra High Capacity of Envisia Ambit Product Enables Chip-Level Synthesis]]> Tue, 07 Sep 1999 00:00:00 -0700 CDNS CDNS <![CDATA[Mentor Graphics' SST Velocity Static Timing Tool Now Supported in Fujitsu's ASIC Design Kit]]> Wed, 16 Dec 1998 00:00:00 -0800 6702 MENT 6702,MENT <![CDATA[HP and VLSI Technology to Provide Design and Development Tools for VLSI's ARM-Based ASICs and ASSPs]]> Mon, 15 Sep 1997 00:00:00 -0700 HPQ HPQ <![CDATA[Sun chooses Summit Design analysis tools; StateAlert and StateScore to be used in processor and ASIC designs for verification and regression testing]]> Wed, 02 Jul 1997 00:00:00 -0700 JAVA JAVA <![CDATA[Synopsys introduces static timing analysis tool for system-on-a-chip verification; PrimeTime launched with unprecedented ASIC vendor sign-off support]]> Mon, 19 May 1997 00:00:00 -0700 <![CDATA[ASIC Semiconductor Supports Mentor Graphics Design for Test Tools]]> Mon, 25 Nov 1996 00:00:00 -0800 MENT MENT <![CDATA[IDE system seeks cut in ASIC development time - NEC Electronics and Microsystem Synthesis KO-Integrated Development Environment development tool - Company Business and Marketing]]> Mon, 12 Aug 1996 00:00:00 -0700 6723 6723 <![CDATA[Crosspoint Solutions joins Intergraph Electronics' ASIC Partners program, supports Version 14.0 of VeriBest Design Tools]]> Wed, 01 Nov 1995 00:00:00 -0800