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cache memory

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches: This paper explores an integrated architectural and circuit-level approach to reducing leakage energy in instruction caches icaches. Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Estimates suggest a five-fold increase in leakage energy in every future generation....; Tags: Semiconductors, Purdue University, transistor, cache memory; White papers 2000-11-10