<?xml version="1.0" encoding="iso-8859-1" ?>
<rss version="2.0" xmlns:s="http://resources.bnet.com/">
<channel>
	<title><![CDATA[cpu and sun sparc Resources | BNET]]></title>
	<link><![CDATA[http://resources.bnet.com/topic/cpu+and+sun+sparc.html]]></link>
	<description><![CDATA[White papers, case studies, business articles, and blog posts relating to cpu and sun sparc]]></description>
	<s:counts start="0" returned="5" found="5" />
	<language>en-us</language>
	<item>
		<title><![CDATA[$179 buys a single-chip, 50-MHz desktop SPARC CPU. (Texas Instruments introduces MicroSPARC) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199211/ai_n17464321]]></link>
		<description><![CDATA[Next-generation, 32-bit SPARC RISC is more than just  high-throughput, superscalar SuperSPARCs or hyperSPARCs or hyperSPARCs  (EDN, June 4, 1992, pgs 89 to 94).  It also includes high-integration,  minimal SPARC [mu]Ps that target mid- to low-end comp    Next-generation, 32-bit SPARC RISC is more than...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 12 Nov 1992 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/cpu.html"><![CDATA[CPU]]></category>
		<category domain="http://resources.bnet.com/topic/desktop.html"><![CDATA[desktop]]></category>
		<category domain="http://resources.bnet.com/topic/sun+sparc.html"><![CDATA[Sun Sparc]]></category>
		<category domain="http://resources.bnet.com/topic/texas+instruments+inc..html"><![CDATA[Texas Instruments Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">TXN</category>
		<category domain="tickers">TXN</category>
	</item>
	<item>
		<title><![CDATA[Superscalar SPARC RISC integrates CPUs, cache controller, and SRAM. (central processing unit) (Cypress Semiconductor introduces CY7C620 multichip module) (Wescon/92 Supplement) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199211/ai_n17464393]]></link>
		<description><![CDATA[Single-chip implementations are not the only form for a  super-scalar RISC SPARC microprocessor ([mu]P).  Cypress  Semiconductor's approach is a multichip module that tightly  integrates a CPU chip with a cache controller and fast static-RAM SRAM  m    Single-chip implementations are not the only...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 12 Nov 1992 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/chip.html"><![CDATA[chip]]></category>
		<category domain="http://resources.bnet.com/topic/cpu.html"><![CDATA[CPU]]></category>
		<category domain="http://resources.bnet.com/topic/cypress+semiconductor+corp..html"><![CDATA[Cypress Semiconductor Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/risc.html"><![CDATA[RISC]]></category>
		<category domain="http://resources.bnet.com/topic/sram.html"><![CDATA[SRAM]]></category>
		<category domain="http://resources.bnet.com/topic/sun+sparc.html"><![CDATA[Sun Sparc]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">CY</category>
		<category domain="tickers">CY</category>
	</item>
	<item>
		<title><![CDATA[CPU boards use SPARC to handle embedded uses. (Force Computers Inc.'s CPU-2E and CPU-2S)(EDN-Product Update) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199205/ai_n18642833]]></link>
		<description><![CDATA[A pair of CPU boards that target embedded and real-time  applications perform the function of a complete  SPARCstation-2-compatible computer.  The CPU-2E is a VMEbus-compatible  board, and the CPU-2S is a board that does not include a system bus.   Bo    A pair...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 07 May 1992 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/board.html"><![CDATA[board]]></category>
		<category domain="http://resources.bnet.com/topic/cpu.html"><![CDATA[CPU]]></category>
		<category domain="http://resources.bnet.com/topic/sun+sparc.html"><![CDATA[Sun Sparc]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[New Intergraph Clipper CPUs aimed at Sparc workstations - central processing units, Scalable Processor Architecture]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EKF/is_n1887_v37/ai_11499252]]></link>
		<description><![CDATA[CHICAGO -- At the Autofact show last week, Intergraph Corp. sought to leapfrog the price/performance of Sun Microsystems workstations with two new Clipper machines, at the same time that it demonstrated the ease with which Intergraph's I/EMS mechanical-design software can now run on Sun's Sparc architecture.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 18 Nov 1991 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/cpu.html"><![CDATA[CPU]]></category>
		<category domain="http://resources.bnet.com/topic/intergraph+corp..html"><![CDATA[Intergraph Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/processor.html"><![CDATA[processor]]></category>
		<category domain="http://resources.bnet.com/topic/sun+sparc.html"><![CDATA[Sun Sparc]]></category>
		<category domain="http://resources.bnet.com/topic/workstation.html"><![CDATA[workstation]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
	</item>
	<item>
		<title><![CDATA[SPARC CPU module offers easy upgrade path from single to multiprocessing. (Cypress Semiconductor's SPARCore CYM6001K, CYM6002K and CYM6003K CPUs) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199110/ai_n17483223]]></link>
		<description><![CDATA[System designers can now tap th 40-Mhz, 29-MIPS power of SPAR  processors and skip the nonrecurring engineering NRE costs normally  associated with designing multiprocessing compute engine for a new  product. Just select from any of three SPARCORE m    System designers can now tap th...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 24 Oct 1991 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/cpu.html"><![CDATA[CPU]]></category>
		<category domain="http://resources.bnet.com/topic/cypress+semiconductor+corp..html"><![CDATA[Cypress Semiconductor Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/processor.html"><![CDATA[processor]]></category>
		<category domain="http://resources.bnet.com/topic/sun+sparc.html"><![CDATA[Sun Sparc]]></category>
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		<category domain="http://rss.financialcontent.com/stocksymbol">CY</category>
		<category domain="tickers">CY</category>
	</item>
</channel>
</rss>
