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	<title><![CDATA[integrated circuit and tool Resources | BNET]]></title>
	<link><![CDATA[http://resources.bnet.com/topic/integrated+circuit+and+tool.html]]></link>
	<description><![CDATA[White papers, case studies, business articles, and blog posts relating to integrated circuit and tool]]></description>
	<s:counts start="0" returned="19" found="19" />
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		<title><![CDATA[Genesys Testware Adds Graphical User Interface to Embedded Test Tool]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2007_May_21/ai_n19155080]]></link>
		<description><![CDATA[FREMONT, Calif. -- Genesys Testware, Inc., a leading supplier of yield, quality and cost optimization tools for nanometer ICs, announced today the addition of a graphical user interface GUI to its embedded test tool ChiptestMakerTM . Currently IC designers develop long and complex scripts for their embedded test tools to...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 21 May 2007 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/genesys+telecommunications+laboratories.html"><![CDATA[Genesys Telecommunications Laboratories]]></category>
		<category domain="http://resources.bnet.com/topic/gui.html"><![CDATA[GUI]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[Haier IC Adopts Mentor Graphics Eldo Simulator as the Standard Tool for Analog Circuit Design]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2006_August_23/ai_n26965669]]></link>
		<description><![CDATA[WILSONVILLE, Ore. -- Mentor Graphics Corporation (Nasdaq:MENT) today announced that Haier IC has adopted the Mentor Graphics EldoR simulator as its standard SPICE simulator for analog circuit design. Compared with other SPICE simulation tools, Eldo offers better convergence and reduced simulation analysis time.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Wed, 23 Aug 2006 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/mentor+graphics+corp..html"><![CDATA[Mentor Graphics Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/spice.html"><![CDATA[Spice]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">MENT</category>
		<category domain="tickers">MENT</category>
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	<item>
		<title><![CDATA[Analog Devices Simplifies IC Selection Process with New Direct Digital Synthesis Online Evaluation Tool]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2006_August_16/ai_n26959883]]></link>
		<description><![CDATA[NORWOOD, Mass. -- New ADIsimDDSTM Tool Simplifies Task of Selecting, Evaluating and Implementing Direct Digital Synthesis DDS Semiconductors in Applications Ranging from Test and Measurement Equipment to Wireless and Satellite Communications]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Wed, 16 Aug 2006 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/analog+devices+inc..html"><![CDATA[Analog Devices Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ADI</category>
		<category domain="tickers">ADI</category>
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	<item>
		<title><![CDATA[Sigrity Enters IC Package Physical Design Market by Acquiring Technology License from Synopsys; Provides Full Spectrum of Tools to Tackle IC Package Design and Analysis Challenges]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2006_Feb_7/ai_n26750563]]></link>
		<description><![CDATA[SANTA CLARA, Calif. -- Sigrity, Inc., the market leader in power and signal integrity software solutions, today announced the acquisition from Synopsys, Inc. of a worldwide perpetual unrestricted license to advanced single and multi-chip IC package design technology, including technology embodied in Synopsys' Encore products. This acquisition also includes assets...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Tue, 07 Feb 2006 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/analysis.html"><![CDATA[analysis]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[Cirrus Logic DSP Conductor Delivers Simple, Powerful Graphic Programming Tool for CobraNet Networked Audio ICs; Creates Powerful Combination with CS496XX CobraNet ICs for New Age of Distributed Audio Networks]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2005_Oct_7/ai_n15679069]]></link>
		<description><![CDATA[NEW YORK -- Strengthening CobraNetTM technology's position as the leading standard for distributing digital audio over Ethernet, Cirrus Logic Inc. (Nasdaq:CRUS) has unleashed DSP ConductorTM, a powerful new graphical programming tool for its flagship CS4961XX CobraNet-based audio system processors.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Fri, 07 Oct 2005 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/dsp.html"><![CDATA[DSP]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/network.html"><![CDATA[network]]></category>
		<category domain="http://resources.bnet.com/topic/programming+tool.html"><![CDATA[programming tool]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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		<title><![CDATA[Sarnoff Introduces Silicon Proven ESD Design Tool Kit for ICs, Matched to Specific Foundry Processes; Allows Users to Design 'First-Time-Right' I/O Sections with High Performance and Optimized, Robust ESD Protection]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EIN/is_2005_May_12/ai_n13697187]]></link>
		<description><![CDATA[PRINCETON, N.J. & GISTEL, Belgium -- Sarnoff Europe (www.sarnoffeurope.com) today announced the TakeCharger Design Kit from Sarnoff Corporation (www.sarnoff.com), a new product that gives fabless semiconductor companies proven, ready-to-use solutions to quickly optimize the electrostatic discharge ESD and high-performance I/O designs of their ICs for specific foundry processes or applications.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 12 May 2005 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/high-performance.html"><![CDATA[high-performance]]></category>
		<category domain="http://resources.bnet.com/topic/i%252fo.html"><![CDATA[I/O]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/sarnoff+corp..html"><![CDATA[Sarnoff Corp.]]></category>
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		<title><![CDATA[Aldec selected as HDL design entry and verification solution for China National IC Base.(Partnership)(Automated Logic Design Company Inc.)(Brief Article)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb6531/is_200404/ai_n25885680]]></link>
		<description><![CDATA[Aldec, Inc., a pioneer in mixed-language simulation and advanced  design tools for ASIC and FPGA devices, announced that its tools have  been selected as the recommended verification solution at the Shanghai  IC Center Shanghai ICC in China.    Aldec, Inc., a pioneer in mixed-language simulation...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 01 Apr 2004 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/partnership.html"><![CDATA[partnership]]></category>
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		<title><![CDATA[Optimizing Chemical Vapour Deposition Processing Through RF Technology]]></title>
		<link><![CDATA[http://jobfunctions.bnet.com/abstract.aspx?docid=103310]]></link>
		<description><![CDATA[This paper describes Digital Equipment Corporation Semiconductor Division's application of real-time process control, excursion detection, and clean optimization on a PECVD Plasma Enhanced Chemical Vapor Deposition wafer processing tool. The purpose of this effort is to reduce test wafers, spare part usage, and tool downtime, while increasing product yield and...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Wed, 05 Nov 2003 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[Integrated Circuit]]></category>
		<category domain="http://resources.bnet.com/topic/wafer.html"><![CDATA[Wafer]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[Tool]]></category>
		<category domain="http://resources.bnet.com/topic/advanced+energy+industries.html"><![CDATA[Advanced Energy Industries]]></category>
		<category domain="http://resources.bnet.com/topic/rf+monitoring+system.html"><![CDATA[RF Monitoring System]]></category>
		<category domain="http://resources.bnet.com/topic/productivity.html"><![CDATA[Productivity]]></category>
		<category domain="http://resources.bnet.com/topic/semiconductors.html"><![CDATA[Semiconductors]]></category>
		<category domain="http://resources.bnet.com/topic/hardware.html"><![CDATA[Hardware]]></category>
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	<item>
		<title><![CDATA[Tool addresses analog-, mixed-signal designs.(leading edge)(Mentor Graphics' ICassemble addition to IC Station)(Brief Article)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200309/ai_n17512291]]></link>
		<description><![CDATA[Mentor Graphics has added the ICassemble tool to its IC Station  product. The tool allows designers to perform top-down floorplanning,  advanced interactive and automatic routing, and chip assembly. Engineers  can now plan, implement, and connect bloc    Mentor Graphics has added the ICassemble tool to...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 18 Sep 2003 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/mentor+graphics+corp..html"><![CDATA[Mentor Graphics Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">MENT</category>
		<category domain="tickers">MENT</category>
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	<item>
		<title><![CDATA[Tools focus on high-speed-pc-board design.(leading edge: what's hot in the design community)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200309/ai_n17488746]]></link>
		<description><![CDATA[CADENCE IS TAKING a system approach to the pc-board market by  focusing its tools to serve the needs of high-speed-pc-board designers.  The company reasons that advanced ICs will need high-speed pc boards, so  it is aiming its pc-board tools to suppor    CADENCE IS TAKING...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 04 Sep 2003 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/board.html"><![CDATA[board]]></category>
		<category domain="http://resources.bnet.com/topic/cadence+design+systems+inc..html"><![CDATA[Cadence Design Systems Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/pc.html"><![CDATA[PC]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">CDNS</category>
		<category domain="tickers">CDNS</category>
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		<title><![CDATA[Software tool makes short work of polyglot IP in SOC ICs.(Leading edge: what's hot in the design community)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_200308/ai_n17512422]]></link>
		<description><![CDATA[EEs WHO DESIGN TESTABILITY FEATURES into SOC (system-on-chip) ICs  and those who design verification and production-test programs for such  devices have to regard Agilent's SmarTest PG program generator  CTL (core-test language) Browser as a work in    EEs WHO DESIGN TESTABILITY FEATURES into SOC (system-on-chip)...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 21 Aug 2003 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/agilent+technologies+inc..html"><![CDATA[Agilent Technologies Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/ip.html"><![CDATA[IP]]></category>
		<category domain="http://resources.bnet.com/topic/software.html"><![CDATA[software]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">A</category>
		<category domain="tickers">A</category>
	</item>
	<item>
		<title><![CDATA[Synopsys unveils power tool for ICs, ASICs - Synopsys's DesignPower CAD software - Product Announcement]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EKF/is_n2032_v40/ai_16263718]]></link>
		<description><![CDATA[GRENOBLE, FRANCE - Synopsys is introducing DesignPower, a tool for analyzing power requirements of IC and ASIC designs early on in the design process. The product is being rolled out at this week's Euro-DAC '94 conference.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 19 Sep 1994 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[AMI introduces Viewlogic interface; mixed-signal design tools ported to Sun - American Microsystems Inc's mixed-signal IC design tool interface]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EKF/is_n2012_v40/ai_15368544]]></link>
		<description><![CDATA[POCATELLO, IDAHO--In a bid to proliferate its mixed-signal design tools, American Microsystems Inc. has introduced an interface linking its Mixed-Signal Design Solution MSDS suite of analog/mixed-signal ASIC design tools with Viewlogic's schematic capture software and ported MSDS to Sun Microsystems SPARCstation platform.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 02 May 1994 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/sun+microsystems+inc..html"><![CDATA[Sun Microsystems Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">JAVA</category>
		<category domain="tickers">JAVA</category>
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	<item>
		<title><![CDATA[LSI Logic extends reach with CoreWare libraries - integrated circuit design tools]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EKF/is_n1999_v40/ai_15058368]]></link>
		<description><![CDATA[MILPITAS, CALIF.--In a bid to extend its library of applications-specific integrated circuits ASICs deeper into the communications and mass storage markets, LSI Logic today plans to roll out three new CoreWare Library elements. All three are immediately available for ASIC designs using LSI's 0.6 micron, LCB300K cell-based process.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 31 Jan 1994 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/lsi+logic+corp..html"><![CDATA[LSI Logic Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
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	<item>
		<title><![CDATA[Tool set joins synthesis with simulation for reliable ASIC design. (application specific integrated circuit) (Mentor Graphics Corp.'s Top Down Design-Solver) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199211/ai_n17464717]]></link>
		<description><![CDATA[Right-first-time silicon, the Holy Grail of the EDA  (electronic-design-automation) industry, is being sought and found on  routine designs. But, below 1-[mu]m-feature size and above 60,000 gates  or a 33-MHz clock rate, advanced ASIC designs tend to     Right-first-time silicon, the Holy Grail of the...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 26 Nov 1992 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/mentor+graphics+corp..html"><![CDATA[Mentor Graphics Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">MENT</category>
		<category domain="tickers">MENT</category>
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	<item>
		<title><![CDATA[IBM cuts E-beam ASIC fab in sub-micron, CMOS shift - reduction in electron-beam application specific integrated circuit production and change from bipolar to complementary metal oxide semiconductor technology - Lithography Tools]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EKF/is_n1935_v38/ai_12761458]]></link>
		<description><![CDATA[EAST FISHKILL, N.Y.--IBM, as part of a significant reordering of its semiconductor production efforts, is sharply cutting its use of direct-write electron-beam lithography for production of low-volume application specific ICs.]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 26 Oct 1992 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/cmos.html"><![CDATA[CMOS]]></category>
		<category domain="http://resources.bnet.com/topic/ibm+corp..html"><![CDATA[IBM Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">IBM</category>
		<category domain="tickers">IBM</category>
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	<item>
		<title><![CDATA[Custom-IC tool sets merge methods: Valid follows Mentor and Cadence in joining top-down with bottom-up techniques. (integrated circuits) (includes a related article on next-generation suites) (product announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199010/ai_n17488542]]></link>
		<description><![CDATA[Custom-IC tool sets merge methods SAN JOSE, CA--Valid Logic Systems  earlier this week became the third broadlinecomputer-aided-engineering  CAE company to release details of a custom-IC tool set that marries  top-down and bottom-up IC layout methodol  Custom-IC tool sets merge methods SAN JOSE, CA--Valid Logic Systems ...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 18 Oct 1990 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/cadence+design+systems+inc..html"><![CDATA[Cadence Design Systems Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/mentor+graphics+corp..html"><![CDATA[Mentor Graphics Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/software.html"><![CDATA[software]]></category>
		<category domain="http://resources.bnet.com/topic/technique.html"><![CDATA[technique]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">CDNS</category>
		<category domain="http://rss.financialcontent.com/stocksymbol">MENT</category>
		<category domain="tickers">CDNS,MENT</category>
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	<item>
		<title><![CDATA[ASIC makers step up software support; Fujitsu, Harris, Motorola introduce third-party suites. (application-specific integrated circuits) (product announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_198908/ai_n17450478]]></link>
		<description><![CDATA[ASIC makers step up software support Three major ASIC suppliers have  introduced design software suites that employ third-party and  proprietary tools linked by a common user interface and operating  protocol.       Back-end data management differs, as   ASIC makers step up...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 24 Aug 1989 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/fujitsu+ltd..html"><![CDATA[Fujitsu Ltd.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/motorola+inc..html"><![CDATA[Motorola Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/software.html"><![CDATA[software]]></category>
		<category domain="http://resources.bnet.com/topic/supplier.html"><![CDATA[supplier]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
		<category domain="http://resources.bnet.com/topic/.html"><![CDATA[]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">6702</category>
		<category domain="http://rss.financialcontent.com/stocksymbol">MOT</category>
		<category domain="tickers">6702,MOT</category>
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	<item>
		<title><![CDATA[Everything's coming up ASICs. (application-specific integrated circuits) (includes related articles on the ASIC business)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_198811/ai_n17455016]]></link>
		<description><![CDATA[Everything's coming up ASICs       Creating successful application-specific ICs ASICs--standard  cells, gate arrays, and programmable logic devices PLDs--doesn't  end with technology prowess.  The successful vendor will also possess a  broad product  Everything's coming up ASICs     ...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 17 Nov 1988 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/asic.html"><![CDATA[ASIC]]></category>
		<category domain="http://resources.bnet.com/topic/cmos.html"><![CDATA[CMOS]]></category>
		<category domain="http://resources.bnet.com/topic/computer+associates+international+inc..html"><![CDATA[Computer Associates International Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/integrated+circuit.html"><![CDATA[integrated circuit]]></category>
		<category domain="http://resources.bnet.com/topic/tool.html"><![CDATA[tool]]></category>
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