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	<title><![CDATA[risc and sun sparc Resources | BNET]]></title>
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	<description><![CDATA[White papers, case studies, business articles, and blog posts relating to risc and sun sparc]]></description>
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		<title><![CDATA[Sun intros heat RISC arena - Sun Microsystems' microSparc IIep embedded SPARC MPUs - Product Announcement]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_m0EKF/is_n2111_v42/ai_18182570]]></link>
		<description><![CDATA[Mountain View, Calif.--Activity heated up in the RISC market last week as Sun Microsystems unveiled a new workstation version of its Sparc architecture and separately introduced an embedded version--microSparc-IIep--at the Embedded Systems Conference in Boston. MicroSparc-IIep will be the first Sparc microprocessor to incorporate the Peripheral Component Interconnect PCI bus...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Mon, 08 Apr 1996 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/risc.html"><![CDATA[RISC]]></category>
		<category domain="http://resources.bnet.com/topic/sun+microsystems+inc..html"><![CDATA[Sun Microsystems Inc.]]></category>
		<category domain="http://resources.bnet.com/topic/sun+sparc.html"><![CDATA[Sun Sparc]]></category>
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		<title><![CDATA[Superscalar SPARC executes as many as three instructions in parallel. (Texas Instruments' SuperSPARC microprocessor) (Wescon/92 supplement) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199211/ai_n17464369]]></link>
		<description><![CDATA[The Texas Instruments' third-generation RISC microprocessors  ([mu]Ps) are the first superscalar implementation of the SPARC RISC  (reduced-instruction-set-computer) processor.  SuperSPARC has a 3.1M  transistor chip (0.8-[mu] BiCMOS) with 36 kbytes o    The Texas Instruments' third-generation RISC microprocessors  ([mu]Ps) are the first superscalar implementation...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 12 Nov 1992 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/microprocessor.html"><![CDATA[microprocessor]]></category>
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		<category domain="http://resources.bnet.com/topic/texas+instruments+inc..html"><![CDATA[Texas Instruments Inc.]]></category>
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		<title><![CDATA[Superscalar SPARC RISC integrates CPUs, cache controller, and SRAM. (central processing unit) (Cypress Semiconductor introduces CY7C620 multichip module) (Wescon/92 Supplement) (Product Announcement)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199211/ai_n17464393]]></link>
		<description><![CDATA[Single-chip implementations are not the only form for a  super-scalar RISC SPARC microprocessor ([mu]P).  Cypress  Semiconductor's approach is a multichip module that tightly  integrates a CPU chip with a cache controller and fast static-RAM SRAM  m    Single-chip implementations are not the only...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 12 Nov 1992 00:00:00 -0800</pubDate>
		<category domain="http://resources.bnet.com/topic/chip.html"><![CDATA[chip]]></category>
		<category domain="http://resources.bnet.com/topic/cpu.html"><![CDATA[CPU]]></category>
		<category domain="http://resources.bnet.com/topic/cypress+semiconductor+corp..html"><![CDATA[Cypress Semiconductor Corp.]]></category>
		<category domain="http://resources.bnet.com/topic/risc.html"><![CDATA[RISC]]></category>
		<category domain="http://resources.bnet.com/topic/sram.html"><![CDATA[SRAM]]></category>
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		<title><![CDATA[Strong embedded-RISC lineup meets cost, integration needs. (reduced-instruction-set computer processors) (buyers guide)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199006/ai_n17454109]]></link>
		<description><![CDATA[Strong embedded-RISC lineup meets cost, integration needs Designers  searching for a reduced-instruction-set-computing RISC processor to  power an embedded-control application have never had such a bountiful  selection.  There are more architectures a  Strong embedded-RISC lineup meets cost, integration needs Designers  searching for a reduced-instruction-set-computing RISC...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 28 Jun 1990 00:00:00 -0700</pubDate>
		<category domain="http://resources.bnet.com/topic/advanced+micro+devices+inc..html"><![CDATA[Advanced Micro Devices Inc.]]></category>
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		<category domain="http://resources.bnet.com/topic/risc.html"><![CDATA[RISC]]></category>
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		<title><![CDATA[RISC camps vie for design wins. SPARC goes furthest: will give you board designs. (reduced-instruction-set computers, Sun Microsystems Inc.'s Scalable Processor Architecture)]]></title>
		<link><![CDATA[http://findarticles.com/p/articles/mi_hb4804/is_199001/ai_n17458817]]></link>
		<description><![CDATA[RISC camps vie for design wins          SPARC goes furthest: will give you board designs     Battling for the hearts--and dollars--of RISC-based workstation  developers, the three major RISC camps are rushing to establish software  compatibility standar ...]]></description>
		<s:doctype><![CDATA[Research articles]]></s:doctype>
		<pubDate>Thu, 25 Jan 1990 00:00:00 -0800</pubDate>
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