SANTA CLARA, Calif. -- Sigrity, Inc., the market leader in power and signal integrity software solutions, today announced the acquisition from Synopsys, Inc. of a worldwide perpetual unrestricted license to advanced single and multi-chip IC package design technology, including technology embodied in Synopsys' Encore products. This acquisition also includes assets...
This paper describes Digital Equipment Corporation Semiconductor Division's application of real-time process control, excursion detection, and clean optimization on a PECVD Plasma Enhanced Chemical Vapor Deposition wafer processing tool. The purpose of this effort is to reduce test wafers, spare part usage, and tool downtime, while increasing product yield and...
FREMONT, Calif. -- Genesys Testware, Inc., a leading supplier of yield, quality and cost optimization tools for nanometer ICs, announced today the addition of a graphical user interface GUI to its embedded test tool ChiptestMakerTM . Currently IC designers develop long and complex scripts for their embedded test tools to...
CADENCE IS TAKING a system approach to the pc-board market by focusing its tools to serve the needs of high-speed-pc-board designers. The company reasons that advanced ICs will need high-speed pc boards, so it is aiming its pc-board tools to suppor CADENCE IS TAKING...
PRINCETON, N.J. & GISTEL, Belgium -- Sarnoff Europe (www.sarnoffeurope.com) today announced the TakeCharger Design Kit from Sarnoff Corporation (www.sarnoff.com), a new product that gives fabless semiconductor companies proven, ready-to-use solutions to quickly optimize the electrostatic discharge ESD and high-performance I/O designs of their ICs for specific foundry processes or applications.
WILSONVILLE, Ore. -- Mentor Graphics Corporation (Nasdaq:MENT) today announced that Haier IC has adopted the Mentor Graphics EldoR simulator as its standard SPICE simulator for analog circuit design. Compared with other SPICE simulation tools, Eldo offers better convergence and reduced simulation analysis time.
NORWOOD, Mass. -- New ADIsimDDSTM Tool Simplifies Task of Selecting, Evaluating and Implementing Direct Digital Synthesis DDS Semiconductors in Applications Ranging from Test and Measurement Equipment to Wireless and Satellite Communications
Mentor Graphics has added the ICassemble tool to its IC Station product. The tool allows designers to perform top-down floorplanning, advanced interactive and automatic routing, and chip assembly. Engineers can now plan, implement, and connect bloc Mentor Graphics has added the ICassemble tool to...
GRENOBLE, FRANCE - Synopsys is introducing DesignPower, a tool for analyzing power requirements of IC and ASIC designs early on in the design process. The product is being rolled out at this week's Euro-DAC '94 conference.
EEs WHO DESIGN TESTABILITY FEATURES into SOC (system-on-chip) ICs and those who design verification and production-test programs for such devices have to regard Agilent's SmarTest PG program generator CTL (core-test language) Browser as a work in EEs WHO DESIGN TESTABILITY FEATURES into SOC (system-on-chip)...
MILPITAS, CALIF.--In a bid to extend its library of applications-specific integrated circuits ASICs deeper into the communications and mass storage markets, LSI Logic today plans to roll out three new CoreWare Library elements. All three are immediately available for ASIC designs using LSI's 0.6 micron, LCB300K cell-based process.
EAST FISHKILL, N.Y.--IBM, as part of a significant reordering of its semiconductor production efforts, is sharply cutting its use of direct-write electron-beam lithography for production of low-volume application specific ICs.
NEW YORK -- Strengthening CobraNetTM technology's position as the leading standard for distributing digital audio over Ethernet, Cirrus Logic Inc. (Nasdaq:CRUS) has unleashed DSP ConductorTM, a powerful new graphical programming tool for its flagship CS4961XX CobraNet-based audio system processors.
ASIC makers step up software support Three major ASIC suppliers have introduced design software suites that employ third-party and proprietary tools linked by a common user interface and operating protocol. Back-end data management differs, as ASIC makers step up...
Everything's coming up ASICs Creating successful application-specific ICs ASICs--standard cells, gate arrays, and programmable logic devices PLDs--doesn't end with technology prowess. The successful vendor will also possess a broad product Everything's coming up ASICs ...
Right-first-time silicon, the Holy Grail of the EDA (electronic-design-automation) industry, is being sought and found on routine designs. But, below 1-[mu]m-feature size and above 60,000 gates or a 33-MHz clock rate, advanced ASIC designs tend to Right-first-time silicon, the Holy Grail of the...
Custom-IC tool sets merge methods SAN JOSE, CA--Valid Logic Systems earlier this week became the third broadlinecomputer-aided-engineering CAE company to release details of a custom-IC tool set that marries top-down and bottom-up IC layout methodol Custom-IC tool sets merge methods SAN JOSE, CA--Valid Logic Systems ...
Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced that its tools have been selected as the recommended verification solution at the Shanghai IC Center Shanghai ICC in China. Aldec, Inc., a pioneer in mixed-language simulation...
POCATELLO, IDAHO--In a bid to proliferate its mixed-signal design tools, American Microsystems Inc. has introduced an interface linking its Mixed-Signal Design Solution MSDS suite of analog/mixed-signal ASIC design tools with Viewlogic's schematic capture software and ported MSDS to Sun Microsystems SPARCstation platform.
TI semiconductors and Fulton eCoupledTM technology to enable contactless power delivery and charging solutions DALLAS, Nov. 17 /PRNewswire/ -- Texas Instruments Incorporated TI announced it is working with Fulton Innovation, LLC Fulton to accelerate development of efficient wireless power solutions that can charge portable devices without...
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